Analog Inputs ──┬── ADC0 (Main Mic) ├── ADC1 (Secondary Mic) ├── ADC2 (ANC/Reference) └── ADC3 (Line-in/Headset detect) ↓ Digital Decimation Filters ↓ ┌─────────────────────────┐ │ Audio DSP (Qualcomm Hexagon, 240 MHz) │ │ - FIR/IIR filters │ │ - Dynamic Range Control │ │ - Sample rate converter │ └─────────────────────────┘ ↓ ┌─────────────────────────┐ │ Hi-Fi DAC (32-bit, 384 kHz) │ │ - DSD direct path │ │ - 4th-order noise shaping │ └─────────────────────────┘ ↓ Class-H Headphone Amp (L+R) ↓ HP_L, HP_R output pins
: It is designed for crystal-clear sound with a high Signal-to-Noise Ratio (SNR) and minimal background hiss. Low Latency
| Parameter | Value | |--------------------------|--------------------------------| | DAC SNR (A-weighted) | 128 dB | | THD+N (DAC) | -108 dB | | ADC SNR (Mic input) | 102 dB | | Headphone Output Power | 2 × 40 mW into 32Ω @ 1% THD | | Supply Voltage (Analog) | 1.8 V / 1.2 V (internal LDO) | | Digital I/O Voltage | 1.2 V – 1.8 V (programmable) | | Package | 81-ball WLCSP (0.4 mm pitch) | wcd9341 datasheet
The WCD9341 is a highly integrated audio codec chip designed for portable and mobile applications. This paper provides an in-depth analysis of the WCD9341 datasheet, highlighting its key features, specifications, and potential applications.
For a full register-level programming guide or timing diagrams, refer to Qualcomm document 80-NL713-XX under NDA. This review is based on public revision 1.4 (2016-08-12) and community-validated measurements. Analog Inputs ──┬── ADC0 (Main Mic) ├── ADC1
The audio DSP provides five user-selectable interpolation filters for PCM (datasheet Table 12):
Speaker protection algorithms (monitoring voltage and current excursions). For a full register-level programming guide or timing
| Ball Range | Signal Group | Description | | :--- | :--- | :--- | | A1-A5, B1-B5 | | Microphone bias voltage (2.0V/2.5V/2.8V selectable). | | C3-C8, D3-D8 | HPH_L, HPH_R | High-fidelity headphone outputs (left/right). | | F1-F10 | VDD_IO | I2S (Inter-IC Sound) and I2C (Inter-Integrated Circuit) control buses. | | J5-J12 | VSS / GND | Analog and digital ground planes. Critical: Split planes are required. | | K1-K8 | SLIMbus | Qualcomm’s proprietary serial bus for audio data. |
The WCD9341 is typically paired with high-end Qualcomm Snapdragon processors to handle complex audio processing tasks. Common pairings include:
For edge AI and smart assistants, the WCD9341 hosts a programmable digital signal processor (DSP). This DSP offloads critical voice tasks from the primary application processor: Multi-microphone beamforming and far-field pickup. Echo Cancellation and Noise Suppression (ECNS).